This application claims the priority of Korean Patent Application No. 2002-29605, filed May 28, 2002, which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit, and more particularly, to a PLL circuit having a wide locked range and a semiconductor integrated circuit (IC) device having the same.
2. Description of the Related Art
In order to obtain a PLL circuit having a wide locked range, a frequency oscillation band of a voltage controlled oscillator (VCO) included in a PLL circuit has to be widened and the sensitivity of the PLL circuit has to be increased within a provided direct current (DC) operational voltage range, i.e., a range between a power supply voltage VDD and a power voltage VSS. When the sensitivity of a PLL circuit increases, an output signal of the PLL circuit becomes sensitive to a noise voltage input into an output voltage of a loop filter so that jitter generated in the output signal of the PLL circuit increases. A noise voltage may be input from a circuit adjacent to the loop filter or a semiconductor device adjacent to the PLL circuit.
FIG. 1 is a block diagram illustrating a conventional PLL circuit. Referring to FIG. 1, a PLL circuit 101 includes a phase/frequency detector 111, a charge pump 121, a loop filter 131, and a voltage controlled oscillation unit 141.
The sensitivity Fvco_sens of an output signal Fvco of the PLL circuit 101 to an output voltage Vfilter of the loop filter 131 is given by Equation 1.Fvco—sens[Hz/V]=[(Vfilter×Kvi)+Idc]×Kosc  (1)
Here, Kvi denotes a current Ivi transform coefficient for an input voltage of a voltage to current (VI) converter, which is included in the voltage controlled oscillation unit 141 excluding an oscillator. Kosc is a frequency variation correlation coefficient of the oscillator for an output current of the VI converter. In addition, it is assumed that the sizes of transistors included in a current mirror of the voltage controlled oscillation unit 141 are the same.
A graph illustrating the sensitivity of a signal Fvco output from the PLL circuit 101 is shown in FIG. 2. With reference to FIG. 2, the output signal Fvco of the PLL circuit 101 varies linearly with an output voltage Vfilter from the loop filter 131. Here, the gradient of the sensitivity 211 is very steep.
Since the gradient of the sensitivity 211 of the output signal Fvco from the PLL circuit 101 is steep, when a noise voltage Vnoise is input to the output voltage Vfilter of the loop filter 131, jitter is increased in the output signal Fvco of the PLL circuit 101.
Referring to FIG. 3, when a noise voltage Vnoise is input into the output voltage Vfilter of the loop filter 131, jitter f1 generated in the output signal Fvco of the PLL circuit 101 increases in proportion to the noise voltage Vnoise.
As described above, although a conventional PLL circuit 101 can attain a wide locked range due to an increased sensitivity 211 of the PLL circuit 101, a jitter f1 generated in an output signal Fvco of the PLL circuit 101 increases when a noise voltage Vnoise is input to an output voltage Vfilter of a loop filter 131.